Catena 4710 Status Report 2019-01-04

Catena 4710 Status Report 2019-01-04

Happy New Year, all!

The Catena 4710 continues to approach production status.  Here are the highlights.

Big highlight: the PDM microphone is working.  This was a bit of an adventure, and I'll go into details below.

On other fronts,we are still waiting for sign-off on releasing certain components to open source. We have another level of management sign-off now. I am hopeful that this process will complete in another few weeks, which will allow MCCI to release the full design RTL. Also, we have the a workflow that builds the various open-source FPGA tools, which means we'll be able to release them at the same time we release the design.

I'll keep posting periodic updates.

--Terry

The PDM to PCM adventure

And now, here's the
  • Decide how to get audio out of the 4710 and over to a PC, so we could analyze and listen to it. There's a 230.4k UART, so decided on base64 encoding, and then cut/paste to a base64 decoder, then import into Audacity.  This workflow was inspired by a blog post by Cheshire Engineering.  However, we decided to use 8k audio and use base64 encoding. Since we like Teraterm, we used that in our project, too.
  • Decide on an approach for converting PDM to PCM (in other words, how to convert a 3 MHz stream of one-bit conversions to a sequence of samples that were "as if" they'd come from a normal analog-to-digital conversion). My initial thought: just integrate the number of ones in 125 microseconds, and use that at the result.
  • Design a set of registers (a hardware API, as it were) for getting the converted data to software.
  • Refactor the RISC-V CPU code (the FPGA Verilog code) so that it's easier to drop in additional modules. This work is not completed yet, but at least the PDM-to-PCM converter Verilog code was written as a module next to the CPU, with a more natural bus interface, rather than buried in the middle of the CPU core as the other peripherals currently are.
  •  Write the Verilog code to implement the audio conversion.
  • Test the design and wrestle with the somewhat primitive Verilog tools.  Fed the design through several different tools, because the synthesis tools will happily compile things without warning you (like connecting an 18-bit port to a 1-bit wire. Fortunately, the Apio project introduced me to Verilator and Iverilog; when stumped, feeding the design through Verilator or Iverilog generally revealed the issue.
  •  Get first audio (yay).  But it sounded bad (sigh).
At this point I could have moved on to the next problem, because I had proved that the low-level hardware was working.  But I wanted to figure out what was going on, and I also wanted to be sure that we had adequate grounding and power supply decoupling. So I did a little more work. After reviewing the literature, I realized that the simple filter I used had no Nyquist filtering -- so everything above 8 kHz was aliasing down into the baseband. PDM microphones have a lot of noise above 8 kHz (scaling 24 dB/octave above 100 kHz according to some references). So I did some more digging.
  • I discovered (and learned about) CIC filters -- these are really very cool, as you can arrange to attenuate data above the pass-band pretty dramatically. Rather than debug in hardware, I built a test-bench implementation in C (including generating a simulated  3 MHz PDM stream), senT the audio to Audacity, made sure it works, then coded Verilog. 
  • Get second audio (yay) and it sounds much better (yay), but now I was getting particular...
  • Find open-source tools (Scilab and a toolbox from TSD Conseil), characterize my filter, discover that... I can improve things a lot by adding one more stage of delay.
That said, to really make the PDM mic work as an audiophile mic requires still more work; a single-stage CIC filter is always going to have aliasing problems, and some work will have to be done to reject the noise. Good project for future work!